In some conventional non-volatile memories (NVMs), high voltages must be applied to bit cells to alter their states. Oversized transistors are used to route high voltages to each bit cell. Wide transistors that support the necessary drive currents typically create larger-than-normal and undesired leakage currents. For example, as the overall area of a transistor is increased to handle these high voltages, leakage currents also increase causing complications during circuit operation. To further compound the issue, NVMs typically utilize high voltages during word and page erase modes resulting in assertion of high voltages across an array of oversized transistors. This results in an aggregate of leakage currents placing a strain on the high voltage supply performance while degrading circuit efficiency.
In some low-power applications, there is an increased sensitivity to leakage currents within circuits that use high voltages for erasing and programming bit cells. High voltage levels are provided using a charge pump, a device that uses a low voltage power source to generate high voltages. Depending on the application, the charge pump and low voltage power source are sized to compensate for current leakage that occurs during high voltage operation. However, supplying additional current to overcome the leakage not only increases the erase and program mode operating currents, it also necessitates making the high voltage generation circuit larger and more complex resulting in increased circuit area and power consumption. The problem of leakage current is further exacerbated through the requirement that certain high voltage circuits must operate at elevated temperatures, e.g. at up to 150° C. This high temperature increases the undesired leakage current to even higher levels.
Several solutions currently employed by some conventional NVMs include increasing threshold voltages of the high voltage devices, creating unique devices or circuits, or back biasing the circuit's substrate with a negative power supply. Each solution presents a design limitation. For example, increasing the threshold voltage of each device is undesirable due to the increase in device size of each transistor which affects the overall performance of associated circuits. An increase in size is almost always necessary for a transistor with higher threshold voltage, since when asserted, these transistors cannot supply as much output current as transistors with lower threshold voltage can. Similarly, introducing a complex circuit design to obviate leakage adds to the overall design complexity and increases the number of fabrication processes. Additionally, back biasing the substrate with a negative power supply would require certain devices of the integrated NVM circuit to be embedded into a separate well. As such, a triple well process and a charge pump would be needed to provide the negative voltage resulting in an increased circuit area and complexity.
Therefore, a device is needed that reduces the effects of leakage current in NVMs while minimizing device size, maintaining moderate circuit complexity, and may be fabricated with minimal processing steps.